Highlight achievements

The demonstrated 3D printed polymer-based impingement jet cooler can enable the customization of the nozzle design to match the power dissipation pattern of the chip in order to increase cooling efficiency, which can be used in different packaging architectures. We successfully demonstrated an 8x8 nozzle array 3D printed multijet impingement cooler with a nozzle diameter of 300 μm, resulting in a nozzle density of 100 per cm2. The experiments indicate that the multijet cooler can achieve a very low thermal resistance of 0.13 K.cm2/W at a flow rate of 1 L/min. The benchmarking study with literature data for impingement coolers with a large range of inlet diameters shows a very good thermal performance of the fabricated cooler for a low required pumping power. The major achievement was highlighted in imec Technology Forum (ITF 2018). Together with my colleagues, our research has been covered by lots of magazines: EE Times, eeNews, 3DIncites, Chip Scale Review, 3D Printing, and Coolingzone.com.

2015.08-2020.09 @ 3D integration program, imec and Thermal-mechanical lab, KU Leuven

This Ph.D. focuses on the modeling, design, fabrication, and characterization of a micro-scale liquid impingement cooler using advanced, yet cost-efficient, fabrication techniques. The main objectives are (a) development of a modeling methodology to optimize the cooler geometry; (b) exploring low-cost fabrication methods for the package level impingement jet cooler; (c) experimental thermal and hydraulic characterization and analysis of the fabricated coolers; (d) applying the direct impingement jet cooling solutions to different applications, such as bare die package, 2.5D interposer package, hot-spots targeted cooling and larger dia package.

II: Embedded microchannel cooling for high heat flux applications

2020.01-Now @ Stanford Nanoheat Lab

  1. Numerical Study of Large Footprint (24 X 24mm2) Silicon-Based Embedded Microchannel-3D Manifold Coolers: 2020.01

  2. Micro-channel Cooling Technique to Minimize Thermal Deformation of the X-ray and High-power Laser Optics, 2020.10

  3. Heterogeneous SiC Power Modules with Active Cooling, 2021.04

III: CMOS Compatible 3D integration of 5-μm TSV Design, Fabrication and Assembly

IV: Performance and Reliability Study of TGV Interposer in 3D Integration

V: HV LED System-on-a Chip (SoC) Packaging Design

Nov 2014 - Jul 2015

EPACK Lab, Hong Kong University Science and Technology

Focus on LED wafer level packaging using 3D integration technologies (TSV, IPD)

  1. Wafer-level bumping process employed from IC packaging technology is implemented in HVLED packaging.

  2. Cu-Snbumps were electroplated on the cascaded LED chips, providing electrical connection and thermal dissipation path.

  3. A robust bonding structure was achieved and the underfill was successfully dispensed under flip-chip structure with a stand-off height of 20 µm